1. Field of the Invention
The invention relates to a method for producing a PMOS transistor, as well as to a PMOS transistor.
2. Description of Related Art
In the field of automobile electronics and industrial electronics, use is often made of circuits that are operated at voltages about 24 Volts. Such circuits are readily realized by employing discrete transistors. With monolithically integrated solutions, conventional technologies (TTL, CMOS, NMOS) entail problems with the dielectric strength of the integrated transistors. This is partly due to the fact that the manufacturing processes have been designed for an operating voltage of about 5 Volts, and partly to the fact that small component geometries and low parasitic resistances are desired.
In order to also satisfy the demand for circuits of higher dielectric strength, rather complex production methods have been developed, such as the BICMOS production method which allows the production of small transistors of low dielectric strength, as well as transistors of great dielectric strength up to a dielectric strength of about 40 to 60 Volts, e.g., output drivers of average capacity. For a BICMOS production process that provides bipolar and CMOS components, about 17 mask planes are required so that the production costs for such a circuit are about twice those of the production process for a standard CMOS circuit.
The CMOS production process developed by ELMOS, Dortmund, allows an operating voltage of up to 12 Volts, due to particularly favorable doping arrangements of the drain diodes. The NMOS transistors produced according to that method, however, are only of limited use for open drain outputs. A dielectric strength of more than 10 Volts would be of particular interest for automobile electronics.
A known method for increasing the dielectric strength of MOS transistors consists in decreasing the drain doping. The best known method is the so-called lightly-doped drain (LDD) with its technological variations. Mostly, these are self-adjusting methods. For example, both sides of the gate are provided with a spacer bar or spacer. Then, a small dosage is implanted. This doping is diffused so deep that the lateral underdiffusion reaches the gate. In the next step, the high drain-source dosage is implanted and annealed. Under the spacer, a region of weak doping, i.e. the desired LDD, is obtained.
The advantage of this method is in the self-adjustment. The width of the leakly doped drain region is determined exclusively by the depth of the first diffusion, the width of the spacer, as well as the depth of the drain source diffusion. No adjustment tolerances occur. Thus, the method is particularly suited for smaller transistors with channel lengths in the range of 1 .mu.m and spacer lengths in the range of 0.5 .mu.m. Because of the limited width of the weakly doped region (about 0.8 .mu.m maximum), the method is not suitable to achieve dielectric strengths of about 30 Volts.
From EP-A 0 148 342, a method is known for simultaneously producing fast short channel and dielectrically strong MOS transistors in VLSI circuits, which allows the simultaneous production of both short channel transistors with high switching speeds and a supply voltage of 5 Volts, as well as analogue transistors with a drain voltage of up to 12 Volts, but with a slower switching speed, the production requiring the least possible number of additional steps. These known transistors do not achieve a dielectric strength beyond 12 Volts either.
The presently known methods are comparatively complex in their technical efforts and, what is most important, they change the time-temperature budget of a CMOS production process so that the production of dielectrically strong semiconductor elements are not compatible with the standard CMOS production process. Therefore, the known methods cannot readily be integrated into an existing production process.
From U.S. Pat. No. 4,908,326, a method for producing a MOS structure is known wherein the spacer is designed with a particular contour for the ion implants.
It is an object of the present invention to provide a method for producing a PMOS transistor with which an extremely high dielectric strength may be obtained without substantial additional efforts in the production process, while maintaining full compatibility with a standard CMOS production process, as well as to provide a PMOS transistor having an extremely high dielectric strength.